? semiconductor components industries, llc, 2002 april, 2002 rev. 1 1 publication order number: mc100e310/d mc100e310 5vecl low voltage 2:8 differential fanout buffer the mc100e310 is a low voltage, low skew 2:8 differential ecl fanout buffer designed with clock distribution in mind. the device features fully differential clock paths to minimize both device and system skew. the e310 offers two selectable clock inputs to allow for redundant or test clocks to be incorporated into the system clock trees. the lowest tpd delay time results from terminating only one output pair, and the greatest tpd delay time results from terminating all the output pairs. this shift is about 1020 ps in tpd. the skew between any two output pairs within a device is typically about 25 ns. if other output pairs are not terminated, the lowest tpd delay time results from both output pairs and the skew is typically 25 ns. when all outputs are terminated, the greatest tpd (delay time) occurs and all outputs display about the same 1020 ps increase in tpd, so the relative skew between any two output pairs remains about 25 ns. for more information on using pecl, designers should refer to on semiconductor application note an1406/d. the v bb pin, an internally generated voltage supply, is available to this device only. for single-ended input conditions, the unused differential input is connected to v bb as a switching reference voltage. v bb may also rebias ac coupled inputs. when used, decouple v bb and v cc via a 0.01 f capacitor and limit current sourcing or sinking to 0.5 ma. when not used, v bb should be left open. ? dual differential fanout buffers ? 200 ps parttopart skew ? 50 ps outputtooutput skew ? 28lead plcc packaging ? the 100 series contains temperature compensation ? pecl mode operating range: v cc = 4.2 v to 5.7 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = 4.2 v to 5.7 v ? internal input pulldown resistors ? q output will default low with inputs open or at v ee ? esd protection: >2kv hbm, >200v mm ? meets or exceeds jedec spec eia/jesd78 ic latchup test ? moisture sensitivity level 1 for additional information, see application note and8003/d ? flammability rating: ul94 code v0 @ 1/8o, oxygen index 28 to 34 ? transistor count = 212 devices device package shipping ordering information mc100e310fn plcc28 37 units/rail mc100e310fnr2 plcc28 500 units/reel marking diagrams a = assembly location wl = wafer lot yy = year ww = work week plcc28 fn suffix case 776 mc100e310fn awlyyww 128 http://onsemi.com
mc100e310 http://onsemi.com 2 1 56 7891011 25 24 23 22 21 20 19 26 27 28 2 3 4 18 17 16 15 14 13 12 v ee clk_sel clka v cc clka v bb clkb q3 q3 q4 v cco q4 q5 q5 pinout: 28lead plcc (top view) q0 q0 q1 v cco q1 q2 q2 clkb q7 q6 nc v cco q7 q6 logic symbol q0 q0 q1 q1 q2 q2 q3 q3 v bb clka clka q4 q4 q5 q5 q6 q6 q7 q7 clkb clkb clk_sel pin description function ecl differential input pairs ecl differential input pairs ecl differential outputs ecl input clock select reference voltage output positive supply negative supply no connect pin clka, clkb; clka , clkb q0:7; q0 :7 clk_sel v bb v cc, v cco v ee nc input clock clka selected clkb selected clk_sel 0 1 logic diagram and pinout assignment warning: all v cc , v cco , and v ee pins must be externally connected to power supply to guarantee proper operation. * all v cc and v cco pins are tied together on the die. function table
mc100e310 http://onsemi.com 3 maximum ratings (note 1) symbol parameter condition 1 condition 2 rating units v cc pecl mode power supply v ee = 0 v 8 v v ee necl mode power supply v cc = 0 v 8 v v i pecl mode input voltage v ee = 0 v v i v cc 6 v i c ode u o age necl mode input voltage ee 0 v cc = 0 v i cc v i v ee 6 6 v i out output current continuous surge 50 100 ma ma i bb v bb sink/source 0.5 ma ta operating temperature range 0 to +85 c t stg storage temperature range 65 to +150 c q ja thermal resistance (junction to ambient) 0 lfpm 500 lfpm 28 plcc 28 plcc 63.5 43.5 c/w c/w q jc thermal resistance (junction to case) std bd 28 plcc 22 to 26 c/w v ee pecl operating range necl operating range 4.2 to 5.7 5.7 to 4.2 v v t sol wave solder <2 to 3 sec @ 248 c 265 c 1. maximum ratings are those values beyond which device damage may occur. 100e series pecl dc characteristics v ccx = 5.0 v; v ee = 0.0 v (note 1) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 55 60 55 60 65 70 ma v oh output high voltage (note 2) 3915 3995 4120 3975 4050 4120 3975 4050 4120 mv v ol output low voltage (note 2) 3170 3305 3445 3190 3255 3380 3190 3260 3380 mv v ih input high voltage (single ended) 3835 4050 4120 3835 4120 4120 3835 4120 4120 mv v il input low voltage (single ended) 3190 3300 3525 3190 3525 3525 3190 3525 3525 mv v bb output voltage reference 3.62 3.74 3.62 3.74 3.62 3.74 v v ihcmr input high voltage common mode range (differential) (note 3) 2.7 4.6 2.7 4.6 2.7 4.6 v i ih input high current 150 150 150 m a i il input low current 0.5 0.3 0.5 0.25 0.5 0.2 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. input and output parameters vary 1:1 with v cc . v ee can vary +0.46 v / 0.8 v. 2. outputs are terminated through a 50 ohm resistor to v cc 2 volts. 3. v ihcmr min varies 1:1 with v ee , max varies 1:1 with v cc . 100e series necl dc characteristics v ccx = 0.0 v; v ee = 5.0 v (note 1) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 55 60 55 60 65 70 ma v oh output high voltage (note 2) 1085 1005 880 1025 950 880 1025 950 880 mv v ol output low voltage (note 2) 1830 1695 1555 1810 1745 1620 1810 1740 1620 mv v ih input high voltage (single ended) 1165 950 880 1165 880 880 1165 880 880 mv v il input low voltage (single ended) 1810 1700 1475 1810 1475 1475 1810 1475 1475 mv v bb output voltage reference 1.38 1.26 1.38 1.26 1.38 1.26 v v ihcmr input high voltage common mode range (differential) (note 3) 2.3 0.4 2.3 0.4 2.3 0.4 v i ih input high current 150 150 150 m a i il input low current 0.5 0.3 0.5 0.25 0.5 0.2 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. input and output parameters vary 1:1 with v cc . v ee can vary +0.46 v / 0.8 v. 2. outputs are terminated through a 50 ohm resistor to v cc 2 volts. 3. v ihcmr min varies 1:1 with v ee , max varies 1:1 with v cc .
mc100e310 http://onsemi.com 4 mc100e310 ecl dc characteristics 40 c 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max min typ max unit v oh output high voltage 1.085 1.005 0.880 1.025 0.955 0.880 1.025 0.955 0.880 1.025 0.955 0.880 v v ol output low voltage 1.830 1.695 1.555 1.810 1.705 1.620 1.810 1.705 1.620 1.810 1.705 1.620 v v ih input high voltage 1.165 0.880 1.165 0.880 1.165 0.880 1.165 0.880 v v il input low voltage 1.810 1.475 1.810 1.475 1.810 1.475 1.810 1.475 v v bb output reference voltage 1.38 1.26 1.38 1.26 1.38 1.26 1.38 1.26 v v ee power supply voltage 5.25 4.2 5.25 4.2 5.25 4.2 5.25 4.2 v i ih input high current 150 150 150 150 m a i ee power supply current 55 60 55 60 55 60 65 70 ma mc100e310 pecl dc characteristics 40 c 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max min typ max unit v oh output high voltage (note 1.) 3.915 3.995 4.12 3.975 4.045 4.12 3.975 4.045 4.12 3.975 4.045 4.12 v v ol output low voltage (note 1.) 3.170 3.305 3.445 3.19 3.295 3.38 3.19 3.295 3.38 3.19 3.295 3.38 v v ih input high voltage (note 1.) 3.835 4.12 3.835 4.12 3.835 4.12 3.835 4.12 v v il input low voltage (note 1.) 3.190 3.525 3.190 3.525 3.190 3.525 3.190 3.525 v v bb output reference voltage (note 1.) 3.62 3.74 3.62 3.74 3.62 3.74 3.62 3.74 v v cc power supply voltage 4.75 5.25 4.75 5.25 4.75 5.25 4.75 5.25 v i ih input high current 150 150 150 150 m a i ee power supply current 55 60 55 60 55 60 65 70 ma 1. these values are for v cc = 5.0 v. level specifications will vary 1:1 with v cc . ac characteristics v ccx = 5.0 v; v ee = 0.0 v or v ccx = 0.0 v; v ee = 5.0 v (note 1) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit f max maximum toggle frequency tbd tbd tbd ghz t plh t phl propagation delay to output in (differential) (note 2.) in (singleended) (note 3.) 525 500 725 750 550 550 750 800 575 600 775 850 ps t skew withindevice skew (note 4.) parttopart skew (diff) 75 250 50 200 50 200 ps t jitter cycletocycle jitter tbd tbd tbd ps v pp minimum input swing (note 5.) 500 500 500 mv t r /t f output rise/fall time (20%80%) 200 600 200 600 200 600 ps 1. v ee can vary +0.46 v / 0.8 v. 2. the differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the differential output signals. see definitions and testing of eclinps ac parameters in chapter 1 (page 112) of the on semic onductor high performance ecl data book (dl140/d). 3. the single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the out put signal. see definitions and t esting of eclinps ac parameters in chapter 1 (page 112) of the on semic onductor high performance ecl data book (dl140/d). 4. the withindevice skew is defined as the worst case difference between any two similar delay paths within a single device. 5. v pp (min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. the v pp (min) is ac limited for the e310 as a differential input as low as 50 mv will still produce full ecl levels at the output.
mc100e310 http://onsemi.com 5 figure 1. typical termination for output driver and device evaluation (see application note and8020 termination of ecl logic devices.) driver device receiver device qd 50 50 v tt q d v tt = v cc 2.0 v resource reference of application notes an1404 eclinps circuit performance at nonstandard v ih levels an1405 ecl clock distribution techniques an1406 designing with pecl (ecl at +5.0 v) an1503 eclinps i/o spice modeling kit an1504 metastability and the eclinps family an1568 interfacing between lvds and ecl an1596 eclinps lite translator elt family spice i/o model kit an1650 using wireor ties in eclinps designs an1672 the ecl translator guide and8001 odd number counters design and8002 marking and date codes and8020 termination of ecl logic devices
mc100e310 http://onsemi.com 6 package dimensions plcc28 fn suffix plastic plcc package case 77602 issue e 0.007 (0.180) tl -m s n s m 0.007 (0.180) tl -m s n s m 0.007 (0.180) tl -m s n s m 0.010 (0.250) tl -m s n s s 0.007 (0.180) tl -m s n s m 0.010 (0.250) tl -m s n s s 0.007 (0.180) tl -m s n s m 0.007 (0.180) tl -m s n s m 0.004 (0.100) seating plane -t- 12.32 12.32 4.20 2.29 0.33 0.66 0.51 0.64 11.43 11.43 1.07 1.07 1.07 2 10.42 1.02 12.57 12.57 4.57 2.79 0.48 0.81 11.58 11.58 1.21 1.21 1.42 0.50 10 10.92 1.27 bsc a b c e f g h j k r u v w x y z g1 k1 min min max max inches millimeters dim notes: 1. datums l, m, and n determined where top of lead shoulder exits plastic body at mold parting line. 2. dim g1, true position to be measured at datum t, seating plane. 3. dim r and u do not include mold flash. allowable mold flash is 0.010 (0.250) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. the package top may be smaller than the package bottom by up to 0.012 (0.300). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. dimension h does not include dambar protrusion or intrusion. the dambar protrusion(s) shall not cause the h dimension to be greater than 0.037 (0.940). the dambar intrusion(s) shall not cause the h dimension to be smaller than 0.025 (0.635). view s b u z g1 x view d-d h k f view s g c z a r e j 0.485 0.485 0.165 0.090 0.013 0.026 0.020 0.025 0.450 0.450 0.042 0.042 0.042 2 0.410 0.040 0.495 0.495 0.180 0.110 0.019 0.032 0.456 0.456 0.048 0.048 0.056 0.020 10 0.430 0.050 bsc -n- y brk d d w -m- -l- 28 1 v g1 k1
mc100e310 http://onsemi.com 7 notes
mc100e310 http://onsemi.com 8 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc100e310/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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